FIG. 1 illustrates a prior art integrated semiconductor memory circuit. As shown, the memory circuit includes a memory array and sensing structure 100, which will be described in greater detail below with respect to FIGS. 2-4. A command decoder 102 receives a command CMD (e.g., read, write, etc.), and decodes the command into control signals for controlling a row decoder 104 and a column decoder 106. The row decoder 104 and column decoder 106 receive the control signals and address information, and generate drive signals based on the controls signals and address information. For example, the row decoder 104 generates word line drive signals to drive word lines WL of the memory array and sensing structure 100. The column decoder 106 generates bit lines select signals BLS for driving bit line selectors of the memory array and sensing structure 100. The data output from the memory array and sensing structure 100 are output on input/output (I/O) lines, and this output data is sensed by an I/O sense amplifier 108.
FIG. 2 shows the constitution of a cell array 1 and data sense circuits 3 connected thereto in the memory array and sensing structure 100. A DRAM cell MC is composed of one MISFET having a channel body in a floating state. This type of memory cell is also referred to more generally as a floating body cell. The structure of a DRAM cell MC using an n-channel MISFET is shown in FIG. 3. As shown in FIG. 3, the DRAM cell MC has a silicon substrate 10, a p-type silicon layer 12 isolated from the silicon substrate 10 by an insulating film 11 such as a silicon oxide film, a gate electrode 14 formed with a gate insulating film 13 there between, and n-type diffusion regions 15 and 16, which are a source and a drain, respectively. The p-type silicon layer 12 between the n-type diffusion regions 15 and 16 serves as a channel body.
The memory cell array 1 is structured as shown in FIG. 4. Specifically, each of the DRAM cells MC has a floating channel body isolated from one another, sources of the DRAM cells MC are fixed at a reference voltage (ground potential), gates of the DRAM cells aligned in one direction are connected to word lines WL, and drains of the DRAM cells aligned in a direction intersecting the word lines WL are connected to bit lines BL.
The DRAM cell MC dynamically stores a first data state in which the p-type silicon layer 12, which is the channel body, is set at a first potential and a second data state in which the p-type silicon layer 12 is set at a second potential. More specifically, the first data state is written in a manner in which high positive level voltages are applied to a selected word line WL and a selected bit line BL to make a selected DRAM cell perform a pentode operation and majority carriers (holes in the case of the n-channel) generated by impact ionization, which occurs near the drain junction, are held in the channel body. This is, for example, data “1”. The second data state is written in a manner in which a high level voltage is applied to the selected word line WL to raise the channel body potential by capacitive coupling while a potential of the selected bit line BL is set at a low level, and a forward bias current is sent to the junction of the channel body and the drain of the selected DRAM cell so as to emit the majority carriers in the channel body into the drain. This is, for example, data “0”. The DRAM cell MC may also be written in the first data state through gate induced drain leakage (GIDL). Here, a negative potential is applied to the word line while a positive potential is applied to the bit line. Again, the source remains fixed at the reference, ground voltage. This causes a high electric field in the gate/drain region to overlap, and tunneling of electrons from valence band to conduction band occurs. The tunneling electrons generate electron-hole pairs and electrons move to the drain while holes move to the body. Thus, the body potential of the transistor rises as with impact ionization; however, the current generated by GIDL is much less than with impact ionization.
As a result of biasing the substrate by the channel body potential, a threshold voltage Vth1 in the case of the data “1”, is lower than a threshold voltage Vth0 in the case of the data “0”. Accordingly, at the time of a data read operation, the data can be judged by detecting a cell current difference caused by a threshold voltage difference.
As will be appreciated, the DRAM cell of this nature eliminates the need for a capacitor to store data, and provides for further reduction in the size of integrated semiconductor memory circuits.
The data storage state is judged by comparing a cell current to a reference current. As a source for the reference current, a dummy cell DMC is prepared as shown in FIG. 2. The dummy cell DMC may be generally designed such that the reference current produced is at an intermediate value between a cell current Icell1 when the DRAM cell is the “1” data and a cell current Icell0 when the DRAM cell is the “0”. However, in FIG. 2, the dummy cell DMC is composed of two MISFETs having the same structure as that of the DRAM cell MC and whose drains are connected in parallel to a dummy bit line DBL provided for every plural bit lines.
The “0” data is written in one MISFET-MC0 and the “1” data is written in the other MISFET-MC1. Gates of these MISFETs-MC0 and MC1 are connected to dummy word lines DWL1 and DWL2 respectively. The dummy word lines DWL1 and DWL2 are selectively driven simultaneously with a selected word line WL at the time of a data sense operation. Accordingly, a reference current Iref passed through the dummy bit line DBL is derived from Iref=Icell0+Icell1. Correspondingly, in data sense circuits 3, a cell current 2.times.Icell, which is double a detected cell current Icell, is generated to be compared with the aforesaid reference current Iref.
As shown in FIG. 2, the data sense circuits 3 are connected to the bit lines BL of the cell array 1 via bit line selecting circuits 2a. The bit line selecting circuits 2a are multiplexers each of which selects one line out of a plurality of the bit lines. In the example of FIG. 1, each of the bit line selecting circuits 2a selects one line out of four bit lines BL0 to BL3 in response to selecting signals BSL0 to BSL3 for the column decoder 106. The plurality of data sense circuits 3 share a reference voltage generating circuit 6 connected to the dummy bit line DBL which is provided for every plural bit lines. The reference voltage generating circuit 6 generates in a reference node RSN a reference voltage corresponding to the aforesaid reference current Iref, which is passed through the dummy bit line DBL and the dummy bit line selecting circuit 2b. Each of first current sense amplifiers 4a includes current mirror circuitry that generates the aforesaid double cell current 2.times.Icell, compares it with the reference current Iref, and generates in sense nodes SN a potential according to the data. Then, second sense amplifiers 4b, each of which detects the difference in the potential between the sense nodes SN and the reference node RSN, are provided.
In addition, between the sense amplifiers 4a and data lines DL (which are connected to the bit lines BL via the bit line selecting circuits 2a) and between the reference voltage generating circuit 6 and a reference data line RDL (which is connected to the dummy bit line DBL via a dummy bit line selecting circuit 2b by controlling a signal DBSL), clamping circuits 5 are provided for suppressing the rise in the voltages of the bit lines BL and the dummy bit line DBL respectively at the time of the data sense operation. The clamping circuits 5 prevent erroneous writing in the DRAM cell MC and the dummy cell DMC at the time of the data read operation, and more specifically, the clamping circuits 5 suppress the voltages of the bit lines BL and the dummy bit line DBL at a low level so that the selected memory cell and the dummy cell perform a triode operation at the time of the data sense operation.